The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a memory system 10 includes memory 12 that may include an array of memory cells 14-1, 14-2, . . . , and 14-x (collectively referred to as cells 14). The memory cells 14 may be located at intersections of rows/wordlines 16-1, 16-2, . . . , and 16-n (collectively referred to as rows 16) and columns/bitlines 18-1, 18-2, . . . , and 18-m (collectively referred to as columns 18). Each cell may store one or more bits of data as logical 1's or a logical 0's and may be individually addressed. A logical 1 may be represented by a supply voltage potential Vdd, and a logical 0 may be represented by a reference voltage potential Vss, such as ground.
A memory control module 20 may apply row and column addresses 26, 27, referred to as address inputs, to row and column address decoders 22, 24. The address decoders 22, 24 may use multi-bit numbers to access a row and column respectively in which a particular memory cell is located.
The address decoders 22, 24 may include programmable logic arrays that select outputs 28, 29 of the address decoders 22, 24 that correspond to the respective rows and columns. All but one of the outputs of each address decoder 22, 24 may be set to 0. Therefore when one of the respective address inputs changes, two outputs also change. The logic arrays may include one or more successive stages of logic gates.
The logic gates may be inverters, AND gates, NAND gates, OR gates, NOR gates, etc. and may include combinations of, for example, complementary metal oxide semiconductor (CMOS) circuits. CMOS circuits may include n- and p-channel transistors (referred to as n- and p-type transistors) that include source, drain, and gate terminals, also referred to as first, second, and control terminals, respectively. Other types of transistors may also be used.
The n- and p-type transistors may act as switches that are either open or closed. Sources and drains of n- and p-type transistors communicate when the devices are closed and do not communicate when the devices are open. An n-type transistor is open when the gate is at a logical 0, and closed when the gate is at a logical 1. A p-type transistor is closed when the gate is at a logical 0, and open when the gate is at a logical 1.
As the number of memory bits increases, the number of successive stages of logic gates may also increase. Each additional stage adds decoding delay.
The first/input stage of an exemplary address decoder 22 may include inverters such that subsequent stages receive address inputs A and complement address inputs A′ of the address information. In other words, when A=0, A′=1 and vice versa. The address and complement address inputs may also referred to as non-inverted and inverted address inputs respectively. For N address inputs, the address decoder may have 2N outputs, so there will be one line at the output for each possible input. The first stage may also be referred to as a predecoder stage and may logically combine address inputs using, for example, one or more AND logic gates.
Address decoders may be static or dynamic and may include static or dynamic CMOS circuits respectively. Outputs of static decoders are logical functions of the inputs. In contrast, a control signal, such as a clock signal, may control outputs of dynamic decoders so that the outputs are not necessarily functions of the inputs.
Referring now to FIG. 2, an exemplary static decoder 22 includes five logic stages 30-34 to identify one of 2N rows or columns based on N address inputs. Where N=9, address inputs A0, A1, . . . , and A8 may be used to identify one of 29 or 512 rows or columns. The first stage 30 may include inverters 36 that invert address inputs A0, A 1, and A8 to generate inverted inputs A′0, A′1, . . . , and A′8. The second stage 31 may include NAND gates 40 that receive combinations of the inverted and non-inverted address inputs. The third and fourth stages 32, 33 may include NOR gates 42 and AND gates 44 respectively that may receive and logically combine outputs of preceding stages. The fifth stage 34 may include inverters 46 that invert outputs of the AND gates 44. Outputs of the fifth stage 34 correspond to decoder outputs.
Referring now to FIG. 3, an exemplary dynamic decoder 22 may include fewer elements than an equivalent static decoder but may switch between decoder outputs based on clock signals 48. A dynamic decoder 22 may include sequential stages of logic gates, such as an input stage 52, a dynamic stage 54, a combination stage 56 and an output stage 58. Similar to static decoder logic, the input stage 52 may include inverters 60, so that subsequent stages receive inverted and non-inverted address inputs A′(0), A(0), etc. The dynamic stage 54 may be controlled by the clock signal 48 and may include sub-stages that also include sequential logic gates. The combination stage 56 may include NAND gates 62 that combine multiple dynamic stage outputs. The output stage 58 may include inverters 64 to generate decoder outputs.
Referring now to FIG. 4, the dynamic decoder of FIG. 3 is a NAND decoder where the dynamic stage 54 includes dynamic NAND sub-stages. Instead of a dynamic NOR sub-stages, the dynamic stage 54 is a NAND to produce the one-hot logic. In FIG. 4, a dynamic NAND stage 54 may receive address inputs, for example, address inputs A(0), A(1) and a clock signal 48. The dynamic NAND stage 54 may include p- and n-type transistors 104, 106 and 108, 110, 112 respectively, and multiple inverters 114, 116, 118.
When the clock signal 48 is low, a setup/precharge phase occurs. In the precharge phase, the output 120 is driven low regardless of address inputs. Also in this phase, p-type transistor 104 may charge so that the output 120 may be at low/connected to Vss. When the clock signal 48 is high, a second phase, which may be referred to as an evaluation phase, occurs. During the evaluation phase, if inputs A(0), A(1) are also high, the output 120 may be pulled high. In other words, if all received inputs A(0), A(1) are high, then sources and drains n-type transistors 108, 110 will conduct, and sources and drains of the p-type transistors 104, 106 will not conduct. Thus a path may be established between the output 120 and Vdd that may pull the output 120 high. Otherwise, the output 120 may remain low due to the feedback loop formed by the p-type transistor 106.
Referring now to FIGS. 5 and 6, an exemplary dynamic NOR decoder 54 receives address inputs (for example, address inputs A(0)-A(3)), each received in a respective n-type transistors 134-137, and a clock signal 48. The n-type transistors 134-137 are connected in parallel between a dynamic/first node 142 and a second node 143 that communicates with Vss.
When the clock signal 48 goes high, it charges a capacitor formed by n-type transistor 150. P-type transistor 155 is turned on, and p-type transistor 152 cuts off the path to the ground node 143 through n-type transistor 133 while inverter 154 pulls node 144 low. In the meantime, node 142 resets to Vss. When a clock signal 48 goes low, n-type transistor 150 dumps the charge it receives when clock signal 48 is high. The charge goes through n-type transistor 152 and is distributed across node 142 and 145. If A(0), A(1), A(2), and A(3) are all receiving low signals, the charge from n-type transistor 150 raises the voltage of node 142 to a point that inverter 161 may flip/pull up node 146, and, in turn, turn on p-type transistor 160. As a result, node 142 may rise to Vdd. This transition propagates from node 142 to node 158, and, thus, a word line is asserted.
In FIG. 6, the voltage of the dynamic node 142 may correspond to the charging voltage of the n-type transistor 150. A waveform 162 illustrates voltage of the dynamic node 142 when the n-type transistor 150 is sufficiently large to charge up the voltage of node 142 to flip inverter 161. The decoder output 158 may represent one of the decoder outputs (for example, decoder output 0). The decoder output 158 may be pulled high when the node 142 follows waveform 162. During evaluation, when the clock signal 48 goes low, and any of the inputs A(0)-A(3) are high, the waveform of Net 142 follows waveform 164, and the output 158 may be pulled low. Otherwise, if all the inputs A(0)-A(3) are low, the waveform of Net 142 follows waveform 162, and the output 158 may be pulled high.
A dotted waveform 163 illustrates an insufficient charge on node 142 that fails to flip inverter 161. The insufficient charge is due to a respective insufficient charge storage capacity of n-type transistor 150. Therefore, a relatively large device area may be required for n-type transistor 150 to produce sufficient charge, and to assure the functionality for the dynamic NOR decoder 54 of FIG. 5. As the width of the decoder increases to 4-bit or more, the total parasitic capacitance on node 142 increases, and a bigger charge storage transistor 150 is also required to match the charge-sharing from node 142. The size of this transistor 150 may become impractical to implement when the width is greater than 4.
Furthermore, as the decoder width increases, the parasitic capacitance on node 142 increases due to longer interconnect and more diffusion capacitance from individual n-type transistors (for example transistors 134-137). Larger device sizes for n-type transistors 134-137 may be needed so that the charge dumped on node 142 may be drained fast enough without reaching a peak value 165. The peak value 165 may be higher than the trip point of the inverter 161 and may result in a false evaluation. However, increasing the device sizes of n-type transistors 134-137 in turn increases the parasitic capacitance on node 142. This tuning process results in a loop that may be difficult to converge.
Referring to FIG. 7, another dynamic NOR decoder 54 includes sources and drains of n-type transistors 202-204 connected in parallel between nodes 206 and 207 respectively. The gates of the transistors 202-204 receive address input signals, for example A(0)-A(3). The decoder 54 also includes p-type transistors 210, 212 that control clocking operations, an n-type transistor 214 that controls evaluate operations, and an n-type transistor 218 that controls screening operations. The gates of the clocking transistors 210, 212 and evaluation transistor 214 receive the clock signal (CLK) at node 48.
Nodes 206, 208 charge to Vdd when the clock signal 48 is low. When the clock signal 48 switches high, voltage present on either node 206 or node 208 is discharged to Vss through the evaluation transistor 214, depending on the logic appearing at the gates of N-type transistor 202-204. If all of the gates of n-type transistors 202-204 receive Vss at their gates, the voltage on node 206 remains at Vdd. The voltage on node 208 drops to Vss as the gates of the screening n-type transistor 218 and the evaluation transistor 214 receive logic high signals at node 206 and node 48. The logic high signals allow transistors 214, 218 to conduct. As a result, a pull-up p-type transistor 240 turns on, connects Vdd and node 206, and holds node 206 at logic high. This operation results in a transition of low to high at output node 233 while output node 234 remains at logic low. On the other hand, if one of the signals of A[0], A[1] or A[2] is high, node 206 discharges and shuts screening n-type transistor 218 while turning on the pull-up p-type transistor 242. As a result, output node 234 switches from logic low to high, and output node 233 remains at logic low. In summary, inverters 230, 232 output complementary signals when CLK rises.
The decoder 54 of FIG. 7 requires a significant setup time for the address input signals to be stable against the rise of CLK, which adds to the cycle-time overhead. The evaluation transistor 214 also doubles the stack height of the N-tree formed by N-type transistor 202-204, and reduces the efficiency of the operation. As a result, the width of the decoder is limited to 3 or 4-bits, and multiple stages of the decoder 54 may be needed for wider decoding. Accordingly, multiple CLK signals with carefully constructed delay tracking elements are required. Also, repeated setup time may be required across the chain of the decoder 54.
Referring to FIG. 8, still another dynamic decoder 250 is illustrated as an example of the implementation using the dynamic AND of FIG. 4. The input width is limited to 3. Therefore, three stages may be required for a 9-to-512 decoding. The decoder 250 includes cascaded/connected in series stages 252, 254, 260 of dynamic AND of FIG. 4. The clock signal 48 synchronizes the first stage 252 so all gates within the stage are evaluated simultaneously. Each subsequent stage 254, 260 receives and logically combines signals from a previous stage to generate decoder outputs, and therefore the decoder 250 may be referred to as a domino decoder.